Current multi-core processors contain multiple compute cores which are connected to an on-die shared cache through a caching bridge. Multi-processor systems which are constructed with multi-core processors maybe referred to as multi-core multiprocessor (MCMP) systems. MCMP systems are becoming increasingly popular in commercial server systems because of their improved scalability and modular design.
Enforcing ordering of transactions between a system interconnect and an internal core interface is a critical requirement to preserve program order behavior in MCMP systems. Thus, a need exists for efficiently implementing global ordering between the system interconnect and the internal core interfaces.